/* ECP: FILEname=fig13_35.make */
# Makefile for following situation:
# tester.c and sub.c both include tester.h
# The source files may also use stuff from
# our library

CC     = gcc
CFLAGS = -O
INCLS  = -I$(HOME)/include
LIBS   = $(HOME)/lib/my_lib.a

OBJS   = tester.o sub.o
EFILE  = tester

$(EFILE): $(OBJS)
		$(CC) $(CFLAGS) -o $(EFILE) $(OBJS) $(LIBS)

$(OBJS): tester.h
		$(CC) $(CFLAGS) $(INCLS) -c $*.c