CDA4101, Assignment 2

Due Tuesday, 3/22

1. Refer to the timing diagram of Fig. 3-38. The time needed from the point where !MREQ is asserted and the data must be stable before it is read can be calculated two ways from the table.
   1. Calculate the time needed using both calculations for a 100MHz bus.
   2. If the memory needs 15 nsec for this measurement, how many wait states are needed to read from the memory on a 100MHz bus?
   3. Calculate the time needed using both calculations for a 200MHz bus.
   4. If the memory needs 15 nsec for this measurement, how many wait states are needed to read from the memory on a 200MHz bus?
2. Refer to Figure 3-46. The precharge phase cannot be issued until two full cycles after the last READ or WRITE operation. The ACTIVATE command must precede the first READ or WRITE to the same bank by two cycles. Data is produced in the next cycle after a READ. Using the maximum amount of (legal) pipelining,
   1. how many bus cycles are needed to read a word from four different rows of bank 0, including the final precharge?
   2. how many bus cycles are needed to read two words from the same row in bank 0 and two words from the same row in bank 1, including the final precharges?
   3. how many bus cycles are needed to read one word from each of the four banks, including the final precharges?
3. Calculate the bus bandwidth to display 1280x1024 full-color video at 30 frames/sec. Assume that the data must pass over the bus twice, once from the CD-ROM to the memory and once from the memory to the screen.
4. The new FIU-PCI Express system has 10 Gbps lanes (gross capacity), in one direction. How many signal wires (not including ground) are needed in one direction for x32 operation? What is the gross capacity for x32 operation, one way (GBps)? What is the net capacity one way, assuming 8/10b? What would be the net capacity if 128/130b is used?
5. The 4 X 3 memory of Figure 3-28 uses 22 AND gates and three OR gates. It also has 11 input, output, and control lines.
   1. Suppose the circuit were expanded to 64 x 16.
      1. How many AND gates would be needed?
      2. How many OR gates would be needed?
      3. How many pins would be coming into and out of the chip?
   2. Suppose the circuit were expanded to 16 x 64.
      1. How many AND gates would be needed?
      2. How many OR gates would be needed?
      3. How many pins would be coming into and out of the chip?
         
6. For the OMAP4430,
   1. What is in the ARMV7 MPU?
   2. Which chips are in the imaging subsection?
   3. What is the purpose of the AES/SHA chip?
7. For the ATmega168,
   1. What is a watchdog timer?
   2. What is debugWIRE?
   3. What is a USART?
   4. What is SPI?
8. For the Core i7,
   1. What is the speed difference between the i7-to-P67 bus and the P67-to-ICH10 bus?
   2. What is the speed difference between a PCIe lane from the i7 and a PCIe lane from the P67?
   3. What is the speed difference between a USB 2.0 port from the P67 and a USB 2.0 port from the ICH10?
9. Write pseudo code for a round-robin bus-arbitration algorithm.
10. Assume DMA is being used to read all 2048 sectors of 512-bytes each in a track on a disk. Each 32-bit DMA transfer takes 1 bus cycle of 5 nsec. It takes one rotation of 8 msec to read the entire track. How many bus cycles per millisecond is the DMA using the bus? If the DMA has higher priority than the CPU, how many cycles per millisecond are left for the CPU?
11. The new FIU-USB has a maximum payload of 3,200,000 bits for an isochronous data packet. Assuming that a device may send only one data packet per frame, what is the maximum bandwidth (in MBps) for a single isochronous device?
12. In section 3.7.2, assume that the memory space is 32K; the EPROM is 2K in size and will be placed at address 18K; the RAM is 4k in size and will be placed at address 26K; the PIO is 4 bytes and will be placed starting at address 7K. Draw the circuit for the !CS lines into the devices. Use full address decoding.
13. Draw the circuit for the "high bit" in Figure 4.6.
14. What would be the byte code for the instruction:
    GOTO -300
    You must show your work for translating -300 into hex.
15. What is the hex microinstruction for the Micro Assembly Language (MAL) instruction,
    MDR = TOS = MDR - H; wr; goto (MBR OR 0x100)?
    You must show the binary equivalent of the above MAL and identify the various parts of the microinstruction, before writing the hex equivalent.
16. What is the Micro Assembly Language (MAL) instruction for the hex microinstruction 142A40897?
    You must show the binary equivalent of the above hex and identify the various parts of the microinstruction, before writing the MAL code.
17. Draw a picture of the stack after each of these instructions:

           ILOAD j
           ILOAD n
           ISUB
           BIPUSH 7
           ISUB
           DUP
           IADD
           ISTORE k
         

18. Translate the following statement into IJVM symbolic instructions (like ILOAD, BIPUSH, ISTORE, etc). Use reasonable integer values for I, J AND K. Assume that the offset of CALCULATE in the constant pool is 0xA2B4. Since we are not implementing object oriented calls, assume that this (the pointer to the current object) is 0 (NULL). Do not make up an implementation for CALCULATE, just call the subroutine. Use the offset to the constant pool to make the call to the calculate routine.

    K = CALCULATE(I, J, 42);

19. Implement IST_ARRAY in Mic-1. It is just like ISTORE except that it has an extra byte that is the number words on the stack to store into consecutive local variables.

    IST_ARRAY varnum byte

    The instruction will store byte number of words from the stack into consecutive local variables, starting with local variable varnum.

    Use symbolic names in conditional branch statements, but supply a table that gives hex addresses for each of these labels. Be sure all the labels have consistent addresses.

Quiz

The quiz for this homework will be on Thursday, March 24.