1. Why are three latches added to the data path in MIC-3?

     2. Why does the book indicate that MIC-3 can do triple the work of MIC-2?

     3. What is meant be a microstep in MIC-3?

     4. What is meant be a RAW (true) dependence?

     5. Why does SWAP3 wait until cycle 5 to start, instead of cycle 3?

     6. Explain why SWAP is faster in MIC-3 than MIC-2.

     7. The data path was broken into three parts. Why is MIC-3 a four-stage pipeline?

     8. What happens to the instructions that have been prefetched after SWAP6?

     9. What two things does each entry in the decoding unit contain?

    10. What is contained in the Micro-operation ROM?

    11. The queuing unit receives an index for the first micro-operation. It then copies sequential micro-operations into the queue (RAM). When does it stop copying?

    12. When does the decoding unit send the next index to the queuing unit?

    13. How does the decoding unit use the IJVM instruction length?

    14. The IFU feeds the Decoding Unit and the registers. When are new bytes fetched into the IFU?

    15. How many MIR registers are in MIC4?

    16. The clock cycle of MIC1 is measured in deltas. How do these deltas correspond to MIC4?

    17. What happens in MIC4 when a micro-operation with the goto-bit is set?