1. Why does the book say that memories have been getting slower for decades, when memory has actually been getting faster?

     2. Give an example in a pipeline where increasing bandwidth also increased latency.

     3. How does a cache improve memory latency?

     4. How do multiple caches improve bandwidth?

     5. If a split cache is used, how many independent accesses to memory are needed?

     6. Specify the usual location for L1, L2 and L3 caches.

     7. What is the relative size and speed of L1, L2, and L3 caches?

     8. What does it mean that L2 and L3 are an inclusive caches?

     9. What is a cache line, with regard to main memory?

    10. Why is a direct-mapped cache called direct mapped?

    11. What is the purpose of the tag field in a cache?

    12. What is the purpose of the LINE bits in an address?

    13. What is the logic for determining if an address is in the cache?

    14. What is a limitation of the direct mapped cache?

    15. What is the advantage of a set-associative cache over a direct-mapped cache?

    16. Explain the Write Through and Write Back for writing to a word that is in the cache.

    17. Exlpain Write Allocation for writing memory that is not in the cache.

    18. Why do some pipelined machines always execute the instruction in the delay slot?

    19. Why do conditional branches slow down a pipeline more than an unconditional branch?

    20. Why do some machines stall when they encounter a conditional branch?

    21. Give an example of a simple branch prediction algorithm.

    22. Explain two ways to recover from a wrong prediction?

    23. Explain how the CPU can use a history table to help determine where to branch?

    24. What is the limitation of a 1-bit prediction table?

    25. Draw a finite state machine for a 3-bit history table. The prediction is changed only after a third wrong prediction.

    26. What can a compiler do to help predict branch behavior?

    27. What is the purpose of profiling a program?

    28. Why is it possible to have a register read multiple times but only written once in the scoreboard file?

    29. Give examples of RAW, WAR, and WAW dependences.

    30. In Figure 4-43, will the program produce the correct result if I2 is allowed to complete before I1?

    31. What is meant by precise interrupts? How does completing instructions out of order affect precise interrupts?

    32. What types of dependences can register renaming remove?

    33. Why do basic blocks contain insufficient parallelism to exploit pipelining effectively?

    34. Explain hoisting, with regard to basic blocks.

    35. Explain why speculative execution needs support from hardware, compiler and architecture.

    36. What could go wrong if an instruction that was executed speculatively cause irrevocable changes in the data path?

    37. What should happen if a speculative instruction causes a cache miss?

    38. What should happen if a speculative instruction causes an exception?

    39. Explain how a poison bit is used.