1. List the three steps that the CPU must do in order to read a memory word. Do not include the steps that the memory does.

     2. Besides miscellaneous and status, list four categories of CPU control pins.

     3. What types of operations do the bus control pins represent?

     4. A CPU might have three control lines to specify one of eight bus operations. The bus might have a separate line for each of the eight actions. What type of circuit is needed to interface the three CPU with the eight bus pins?

     5. What happens to bus skew as the speed of the bus increases?

     6. What is the advantage of a multiplexed bus?

     7. How does a multiplexed bus affect memory writes?

     8. What is the bus cycle length on a 100MHz synchronous bus?

     9. In Figure 3-38 (a), why are MREQ and RD asserted so late in the first clock cycle?

    10. Which device asserts the WAIT line?

    11. According to Figure 3-38 (b), what is the earliest that MREQ can be asserted after the start of the read cycle?

    12. Referring to the signals in Figure 3-38 (b), explain why a memory read cannot be done in two cycles.

    13. How do TM, TRL and TDS determine the time that the memory has to respond?

    14. Why are synchronous buses bad when considering that devices get faster all the time?

    15. Explain a full-handshake when completing a read on an asynchronous bus.

    16. In a daisy chained bus arbiter, which device has the highest priority for gaining the bus?

    17. How can a bus accept line speed up the bus?

    18. If the CPU accesses memory on the I/O bus, why does the CPU get the lowest priority?

    19. Explain how a bus could implement decentralized arbitration with only three lines.

    20. Explain how a block read is faster than reading each word individually.

    21. Explain why a read-modify-write cycle is necessary in order to control the bus for a longer period of time.

    22. Explain what an interrupt vector is.

    23. What was the maximum throughput for the ISA, 8.33MHz bus?

    24. What was the maximum throughput for the EISA, 33.33MHz bus?

    25. What is the minimum throughput for full motion, color video?

    26. What was the maximum throughput for the 32-bit, PCI, 33MHz bus?

    27. What was the maximum throughput for the 64-bit, PCI, 66MHz bus?

    28. What is the maximum throughput of the Core i7 memory bus?

    29. What is the maximum throughput of the Core i7, on-board, PCIe bus?

    30. What types of devices does a PIO interface with?

    31. How is the latch associated with each port used in a PIO?

    32. How are the data lines used in a PIO?

    33. How can multiple PIO chips be selected from the same set of address lines?