A question with a * means the answer is not directly in the book. You will have to surmise the answer from other information in the book.
	 
	 1. Is the IJVM a RISC or CISC architecture?

     2. Define the state of a microprogram.

     3. Define the data path for the CPU.

     4. List the names for the 6 control lines to the ALU.

     5. In Figure 4-2, explain why all the control lines are 1 when performing B - A. 

     6. Figure 4-2 lists one way to obtain B from the ALU. Indicate the control lines for a different way to obtain B from the ALU.

     7. *In Figure 4-2, why is ENA set when calculating NOT B? Find other examples of instructions that have strange settings.

     8. *Figure 4-2 shows the control signals for B-A. What would be the control signals for A-B?

     9. How is data entered into the H register?

    10. *The shifter in Figure 4-1 has two control lines. The book describes two functions for the shifter. How many functions does the shifter support? Surmise the missing functions.

    11. Why is it essential that registers are loaded from the C bus using an edge-triggered flip-flop and not a latch?

    12. At what point in the data path timing are the ALU and shifter disabled?

    13. How many explicit timing points exist in one clock cycle of the data path?

    14. Which register is used to read data into the MDR?

    15. Which register is used to read data into the MBR?

    16. Which registers do not have two control signals for output to the B bus and load from the C bus?

    17. The MAR and PC both hold addresses for memory. What is different about how these addresses are interpreted by the IJVM?

    18. The MBR is an 8-bit register. Explain the two ways it can be loaded onto the B bus.

    19. How long does it take to read memory in the IJVM?

    20. Why are there 9 bits in the microinstruction for writing to a register from the C bus, but only 4 bits for loading the B bus?

    21. Name the two registers that are used to access the control store.

    22. What happens as soon as the clock goes low (delta w subcycle)?

    23. What happens in the delta x subcycle?

    24. What happens in the delta z subcycle?

    25. When are the N, Z and MPC registers loaded?

    26. How do JAMN and JAMZ affect the MPC?

    27. Why doesn't it make sense for the next address field to have a 1 in the high bit if JAMN or JAMZ are set?

    28. What effect does the JMPC bit have on the next address?