Mic-4 Information

MIRs

There are four microinstruction registers because there are four instructions that have control of the data path at any instant.

IFU

The instruction fetch unit works as it did in Mic-2.

Decode Unit

The Decode Unit contains a table that is indexed by the byte code of an ISA instruction. An entry in the table has the location in the Micorinstruction ROM of the starting address for this ISA instruction, and it has the length of the ISA instruction.

• Since the ROM is now sequential, the decode is more complicated. In Mic-1 and Mic-2, the byte code for an ISA instruction was the address of its first microinstruction. In Mic-1, the first 256 entries in the ROM were the starting microinstructions for each of the 256 possible op codes. This is no longer the case. For instance, IADD is op code 0x60, and in the full JVM, there is an ISA instruction that has an op code of 0x61, let's call IXYZ. If we assume that iadd1 is still at 0x60, then iadd2 would have to be at location 0x61, which contradicts the fact that IXYZ needs to start at 0x61. This means that IXYZ would need a translation of 0x61 into its starting address in the ROM.
• In Mic-1, the next ISA instruction to be processed wasn't fetched until after the current one was nearly complete. This process is too slow for a pipelined machine. By knowing the length of the current ISA instruction, the Decode Unit can determine the location of the next ISA instruction in the IFU before the current ISA instruction is complete. In fact, it can load the microinstructions for the next ISA instruction before the current one even begins to act upon the data path.

Microinstruction ROM and Queuing Unit

• The microinstructions have a different format than in the previous architectures.
• The microinstructions are organized sequentially: all the micro instructions for an ISA instruction are in successive memory locations.
• The Queuing Unit loads instructions from the Microinstruction ROM into the queue. The Queuing Unit receives the starting address of a micro sequence from the Decode Unit. The Queuing Unit then loads sequential instructions from the ROM into the queue until it encounters an instruction with the final bit set. The final bit is a signal to the Queuing Unit to stop loading sequential instructions from the ROM, and to get the starting address of the next micro sequence from the Decode Unit.
• There is no longer a JMPC bit, nor a goto(MBR) instruction. An instruction that had a goto(MBR) in Mic-2, would have the final bit set in the microinstruction ROM in Mic-4. This has the same effect as the goto(MBR) instruction: the starting address of the next micro instruction is retrieved from the Decode Unit.

  Mic-2		Mic-4
  dup1	MAR = SP = SP + 1	dup1	MAR = SP = SP + 1
  dup2	MDR = TOS; wr; got (MBR1)	dup2	MDR = TOS; wr; final

  Notice that the instruction is nearly the same in Mic-2 and in Mic-4, except that dup2 had the final bit set in Mic-4.

• Conditional branch instructions are split into two instructions.
  1. The first instruction is used to set the condition codes. It has the same format as any other instruction that controls the data path. For example:
     Z = MDR + H
  2. The second instruction contains the JAM bits and the NEXT_ADDRESS field. If the jump is taken, then the NEXT_ADDRESS will point to the next miscroinstruction to be loaded into the queue. If the jump is not taken, then the next sequential instruction in the ROM will be loaded. These instructions have a different format and are not sent through the MIR registers. They will have the goto bit set in the ROM. The goto bit indicates that the microinstruction has a different format and that it should not be loaded into the queue. The queuing logic must wait until the previous instruction that sets the condition codes progresses to MIR4. At that time, the condition codes will be set, and the queuing logic can determine which microinstruction to load into the queue.

     Mic-2		Mic-4
     iflt1	MAR = SP = SP - 1; rd	iflt1	MAR = SP = SP - 1; rd
     iflt2	OPC = TOS	iflt2	OPC = TOS
     iflt3	TOS = MDR	iflt3	TOS = MDR
     iflt4	N = OPC; if (N) goto T; else goto F	iflt4	N = OPC
     		iflt5	if (N) goto T
     F	H = MBR2	iflt6	H = MBR2
     F2	goto(MBR1)	iflt7	final

     Notice the instruction iflt5 in Mic-4. Because there is a goto in iflt5, it would have the goto bit set in the ROM. This is a signal to the Queuing Unit to stop loading microinstructions into the queue. When iflt4 finally reaches MIR4, then the Queuing Unit will load iflt6 or T into the queue, depending on the condition codes.

• There is no longer a NEXT_ADDRESS field, except in the conditional branch instructions.
• There are no longer jumps within the microcode, except for the conditional branch instructions. For example, in Mic-2, the wide_iload sequence has a jump to iload2. In Mic-4, the instructions would be duplicated in wide_iload and in iload.

  Mic-2
  wide_iload1	MAR = LV + MBRU2; rd; goto iload2	iload1	MAR = LV + MBR1U; rd
  		iload2	MAR = SP = SP + 1
  		iload3	TOS = MDR; wr; goto (MBR1)
  Mic-4
  wide_iload1	MAR = LV + MBRU2; rd	iload1	MAR = LV + MBR1U; rd
  wide_iload2	MAR = SP = SP + 1	iload2	MAR = SP = SP + 1
  wide_iload3	TOS = MDR; wr; final	iload3	TOS = MDR; wr; final