Tentative schedule

No. Day Date Topics Textbook Reading
1
Mon 1/7 Review topics from CDA3103 ("Boolean and Digital Logic", "Instruction Set Architecture")
2
Wed 1/9 Hierarchy of virtual machines, interpretation vs translation, logical equivalence of software & hardware, components of a computer 1-13, 39-50, LN-1
3
Mon 1/14 CPU interpretation cycle, parallel architectures, pipelining (hazards) 55-73, LN-2
4 Wed 1/16  endian, Memory, error correction (SEC & DED) 73-82, LN-3, LN-4
  Mon 1/21  Martin Luther King's Day - University closed  
5 Wed 1/23 Cache, RAID, I/O devices, modems, unicode 82-141, LN-5, LN-6
6 Mon 1/28 Transistor, logic gates, multiplexer, demultiplexer, encoder, decoder, circuit design & reduction, boolean algebra, Karnaugh maps, Comparator, PLA
shifter, adder, ALU
147-163, LN-7, LN-8
163-167, LN-9
7 Wed 1/30 Clock, latch, flip-flop, memory organization, CPUs, Bus, synchronous, asynchronous, arbitration, interrupt control 168-201, LN-10
8 Mon 2/4 PCI bus, USB bus, Parallel I/O, memory-mapped I/O 215-236, LN-11
9 Wed 2/6 Data path, control signals, micro instructions, micro architecture
MicArchBasics_video, MicArchBasics_notes
243-258, LN-15
10 Mon 2/11 Local addressing, frame pointer register, IJVM instruction set and its semantics 258-261, LN-18
11 Wed 2/13 IJVM semantics, Mic-1 architecture
Mic-1_Arch_video, Mic-1_Arch_notes
262-267 LN-16, LN-17
12 Mon 2/18 Microprogram for Mic-1
Mic-1_Microprogram_video, Mic-1_Microprogram_notes
262-282, LN-20
13 Wed 2/20 Interpretation of INVOKEVIRTUAL, IRETURN, WIDE
Mic-1_Method_video, Mic-1_Method_notes
267-282, LN-20, LN-21
14 Mon 2/25

Mid-term exam

Chs. 1 - 4.3
15 Wed 2/27 Mic-2 (IFU, 3-bus), Mic-3 (4-stage), Mic-4 (7-stage) architectures
Mic-1_SimDemo_video, Mic-1_SimDemo_notes
283-303
16 Mon 3/4 Microprogram for Mic-2 294-295
17 Wed 3/6 Cache organization, direct-mapped cache, branch prediction 304-310
  Mon 3/11   Spring Break  - No class  
  Wed 3/13   Spring Break  - No class  
18 Mon 3/18 branch prediction (static and dynamic), pipeline hazards 310-315, LN-3
19 Wed 3/20 multiple instruction execution: scoreboard (in-order) and Tomasulo (out-of-order with register renaming), speculative execution 315-323
20 Mon 3/25 Review all concepts of micro architecture
21 Wed 3/27 RISC architecture: register file, overlapping register windows, CWP, register file overflow/underflow, WIM RISC Architecture
22 Mon 4/1 Expanding opcode, addressing modes, stack addressing (infix to postfix and postfix evaluation) 365-367, 376-379, LN-22
23 Wed 4/3 Instruction types, Flow control, co-routines, trap, interrupt (nested interrupts, interrupt priority, mask bit) 386-397, 404-417
24 Mon 4/8 Parallel architectures, on-chip parallelism
553-556, 562-574
25 Wed 4/10 Coprocessors: network-, media-, and crypto- processors 574-586
26 Mon 4/15 Shared-memory multiprocessors: taxonomy, memory semantics, snooping caches, shared-memory cache coherence MESI protocol, UMA, NUMA, COMA multiprocessors 586-616
27 Wed 4/17 Message-passing multicomputers: topology, MPP, cluster computing, communication, scheduling, Google architecture, Review 616-636, LN-3

Mon 4/22

Final exam: 7:15pm - 9:15pm

Chs. 4, 5, 8