CDA-4101 Lecture 22 Notes

• The Mic-1 architecture supports only one data type: 32 bit, two's complement integers.
• Since the hardware cannot be changed once it is built, any other data types desired would have to be done in software.
• The IJVM language has the following data types:
  • 32 bit, two's complement integers.
  • 8 bit, two complement integers (e.g., BIPUSH)
  • 16 bit, two complement integers (e.g., branch displacements)
• The microcode converts all of these to 32 bit, two's complement integers internally.
• Thus, the ISA can have data types not found on the hardware.
• However, for every data type the hardware supports, there is usually ISA level support as well.

• Signed Integers: 8, 16, 32 and 64 bits (two's complement)
• Unsigned Integers: 8, 16, 32 and 64 bits
• Floating Point: single and double precision
• Binary Coded Decimal
  
  
• Often there will be separate registers for integer and floating point numbers

• Characters: ASCII (8 bits), UNICODE (16 bits)
• Strings: some ISA's have instructions for these, though the hardware will at best store characters
• Boolean value: need only one bit, sometimes use a bit map
• Pointers (i.e., machine address)
  
  
• Note that although the Mic-1 holds pointers in its registers, aside from when they are in the MAR or PC register and connected to the memroy address lines, there is no hardware support for pointers. (they are added as if two's complement numbers)

Some machines have all instructions the same length, others variable length Am advantage of them all being the same length is easier decoding A disadvantage of this is wasted space, since all instructiosn need to accomodate the longest one.

• For a given instruction format length, there is a trade-off between the number of bits used for the op-code and the number used for operands (e.g., addresses)
  • More op-code bits means more instructions
  • More address bits means more addressable locations
• By using specific prefixes of the op-code, you can get varying number of variable length op-codes

• Suppose we have 16 bit instruction lengths
• We want:
  • 14 op-code for instruction that take 12 bits addresses
  • 7 op-codes that will take a 10-bit address
  • 8 op-codes that will take an 7-bit address

0000  aaa aaaa aaaa
0001  aaa aaaa aaaa
0010  aaa aaaa aaaa
0011  aaa aaaa aaaa
0100  aaa aaaa aaaa
0101  aaa aaaa aaaa
0110  aaa aaaa aaaa
0111  aaa aaaa aaaa
1000  aaa aaaa aaaa
1001  aaa aaaa aaaa
1010  aaa aaaa aaaa
1011  aaa aaaa aaaa
1100  aaa aaaa aaaa
1101  aaa aaaa aaaa


    

1110 00  aa aaaa aaaa
1110 01  aa aaaa aaaa
1110 10  aa aaaa aaaa
1110 11  aa aaaa aaaa
1111 00  aa aaaa aaaa
1111 01  aa aaaa aaaa
1111 10  aa aaaa aaaa


    

1111 1100  0  aaa aaaa
1111 1100  1  aaa aaaa
1111 1101  0  aaa aaaa
1111 1101  1  aaa aaaa
1111 1110  0  aaa aaaa
1111 1110  1  aaa aaaa
1111 1111  0  aaa aaaa
1111 1111  1  aaa aaaa

• Typically, most bits of an instruction are for specifying where the operands of the instruction come from. (not really true in IJVM)
• When you want to instruct a machine to add, it will need to know three things:
  1. Where is the first operand
  2. Where is the second operand
  3. Where does the result go
• For the stack-based IJVM, the ADD instruction has all three of these implicitly defined: on the stack.

• Since most machines are not stacked based, they need other means of specifying operands and their destination.
• If memory addresses are 32 bits, then this means 96 bits, plus the op-code which would be over 100 bits for an instruction (far too big)
• If we only allow adding registers, and we have 32 registers, then we can reduce this to 15 bits (5 bits to address a register) plus the op-code

    ADD R1,R2,R3       # same as R1 = R2 + R3 or R3 = R1 + R2
    

• We can reduce this further if we make one or more of the operands implicit in the instruction.

    ADD R1,R2      #  same as R1 := R1 + R2
    

• An designated accumulator register can make it even simpler (though this has too many disadvantages nowadays)

    ADD R1      #  same as ACC := ACC + R1
    

• The IJVM is the extreme case where we have zero operands in the instruction

• We have seen using a full memory address as an operand requires a lot of bits, while using a register address requires fewer.
• The addres in these cases are fully determined at compile/assemble time.
• Recall in the Mic-1 implementation of IJVM, the branching points were not memory addresses, but diplacements.
• The IJVM displacements are unchanged regardless of where in memory the code is actually located, since it is relative to the current PC value.
• Also, method calls used a similar displacement for locating the method address: the displacement is off the CPP register and thus determined at run-time, not complile/assemble time.
• There are many similar addressing techiques which aim to allow:
  1. shorter address specifications
  2. dynamic address calculations

• Here is where the operand is in the instruction itself (e.g., BIPUSH)

      MOV R1,4
    

• the advantage is that it does not require any extra memory reference: it is fetched with the instruction
• the disadvantage is that only a constant can be specified this way
• note that there needs to be something about the op-code that will let it know if the '4' is a constant or an address or a register number

      MOV R1,R4
    

• At the assembly language level, the same mnemonic could be used, but the assembler would translate this into the proper op-code that would differentiate bwteen the two type

memory address encoded directly in the instruction value can change, but address determined at compile/assemble time can only really be used for global constants

• a.k.a., register mode
• like direct addressing, but instead of the instruction containing a memory address, it contains a register address (i.e., register number)
• Many of the previous examples used register addressing

      MOV R1,R4
    

• this is the most common type of addressing
• in load/store architectures (e.g., UltraSPARC II) all instructions use this mode exclusively (except the load and store instructions)

the memory address of the operand is stored in a register, and the register number is stored in the instruction Here's some generic assembly code for summing all elements of an array A MOV R1,#0 ; accumulate the sum in R1, initially 0 MOV R5,#A ; R5 = address of the array A MOV R3,#A+4096 ; R3 = address of first word beyond A LOOP: ADD R1,(R5) ; register indirect through R5 to get operand ADD R5,#4 ; increment R5 by one word (4 bytes) CMP R5,R3 ; are we done yet? BLT LOOP ; if R5 < R3, we are not done, so continue note the special assembly language syntax for this mode of addressing note the separation of the comparison from the branch: the comparison will set status bits, the branch uses the current status bits to branch (IJVM rolls both these into one instruction)

• Address is given as an offset (displacement) to an address held in a register
• this is exactly what we used to reference local variables and parameters in IJVM where the address was in the LV register.
• You can even invert this, where the memory location is in the instruction, and the offset is in a register
• example of computing the pairwise "AND" of two arrays to see if there is at least one non-zero pair: uses indexed addressing with offsets in registers:

  MOV R1,#0 ; accumulate the OR in R1, initially 0 MOV R2,#0 ; R2 = index, i, of current product: A[i] and B[i] MOV R3,#4096 ; R3 = first index value not in use LOOP: MOV R4,A(R2) ; R4 = A[i] AND R4,B(R2) ; R4 = A[i] AND B[i] OR R1,R4 ; OR all boolean products into R1 ADD R2,#4 ; i = i + 4 (stpe in units of one word (4 bytes) CMP R2,R3 ; are we done yet? BLT LOOP ; if R2 < R3, we are not done, so continue

• note the special indexed addressing syntax

• memory address is computed by adding two registers plus maybe a possible offset
• one of the registers serves as the base address, while the other serves as the offset
• e.g.,

  MOV R1,#0 ; accumulate the OR in R1, initially 0 MOV R2,#0 ; R2 = index, i, of current product: A[i] and B[i] MOV R3,#4096 ; R3 = first index value not in use MOV R5,#A ; R5 = address of A MOV R6,#A ; R6 = address of B LOOP: MOV R4,(R2+R5) ; R4 = A[i] AND R4,(R2+R6) ; R4 = A[i] AND B[i] OR R1,R4 ; OR all boolean products into R1 ADD R2,#4 ; i = i + 4 (stpe in units of one word (4 bytes) CMP R2,R3 ; are we done yet? BLT LOOP ; if R2 < R3, we are not done, so continue

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